Since the density of circuitry on a chip continues to increase, while the number of IO pins of a chip remains small a serious escalation of complexity is caused and testing is becoming more cost intensive. Integrated circuits Ics should be tested before and after packaging, after mounting on a board and periodically during operation. Different testing methods are necessary for each case.
FIG. 1 shows a test equipment according to the state of the art. The devices to be tested (DUT) are connected to a performance test board (PTB) which is connected to a test system. The IO pins of the device under test are connected to the Performance Test Board to perform predetermined testing procedures. The Performance Test Board is exchangeable for performing different tests for different kinds of devices under test.
FIG. 2 shows the test system according to the state of the art in more detail for one device under test. The device under test (DUT) is connected via the Performance Test Board to the test system. The test system comprises a test logic for generating and evaluating test signals. The device under test is connected via the Performance Test Board by means of a control bus, data bus and an address bus to the test logic. During the test the device under test (DUT) is supplied with power by means of internal power-supply sources (IPS) within the test system. The test system according to the state of the art comprises N internal power supply sources.
To decrease testing costs as many devices under test (DUT) as possible are connected in parallel to the Performance Test Board (PTB). A typical Performance Test Board according to the state of the art is provided for testing eight devices under test (DUT) at the same time. Accordingly several internal power supply sources (IPS) of the test system are connected in parallel within the Performance Test Board to supply all devices under test with sufficient operation current. The devices under test (DUT) are for instance memory modules (DIMMs). The possibility of parallel testing of multiple memory modules is more and more limited by the maximum operation current Iop available from the test system's internal power supplies (IPS). The reason for that is that the memory size of the multiple memory modules is rising continuously and the operation clock frequency fclk is also increasing. Consequently the operation current Iop of one memory module (DIMM) or device under test (DUT) is continuously increasing. Since the number N of internal power supplies IPS of the state of the art test system equipment is limited the number of devices under test (DUT) connected to a conventional Performance Test Board PTB according to the state of the art as shown in FIG. 2 is decreased to supply all remaining devices under test (DUT) with a sufficient operation current. Since the number of devices under test (DUT) connected to a Performance Test Board at the same time is limited and has even to be diminished for increasing the operation current Iop required by each device under test (DUT) the testing costs when using a conventional Performance Test Board PTB are increasing rapidly.
The exchange of a already existing test system having a predetermined number (N) of internal power supply sources IPS by a new test system having more internal power supply sources is in most cases not profitable since the costs of a new test system are very high.
A further trend in the development of integrated circuits ICs is that the supply voltages VDD tend to decrease. One reason for that is that because of the increasing operation currents Iop the dissipation heat of one integrated circuit IC is also increasing when the supply voltage VDD is kept constant. By decreasing the supply voltage VDD the dissipation power P of an IC is kept with an certain limit. With the development of memory module generations such as single data rate (SDR) DRAMs to double data rates (DDR) DRAMs or even DDR2 the power supply voltages VDD have dropped from 3.6 volts to 1.8 volts while the operation current Iop has more then doubled. The typical test equipment to test the system comprises N=64 internal power supplies IPS to test eight devices under test (DUT) connected to the Performance Test Board PTB at the same time. Accordingly for each device under test DUT eight (N=8) internal power supplies sources (IPS) are provided each generating typically an operation current of 800 mA. Since eight internal power supply sources IPS are connected in parallel each device under test DUT can be supplied with a maximum current of 6.4 Amp. Because of the increasing memory sizes and the increasing operation clock frequencies fclk in many cases a current of 6.4 Amp. is not sufficient since the current requirement of a device under test DUT exceeds this limit.